DACs, including current steering DACs, are used to convert time varying digital input signals to analogue output signals. The digital signals typically are provided from digital signal processing circuits, and the digital signal comprises a plurality of consecutive data samples provided to the DAC at a data rate, which is the rate or sampling frequency at which an analogue signal is sampled to produce the data samples of the digital signal. In current steering DACs, typically, the data samples are sequentially converted to respective current signals which are proportional to the values of the corresponding data samples. The current signals are sequentially steered by the DAC through a load resistor, across which an analogue voltage output proportional to the values of the data samples is developed. The current signals are steered through the load resistor for respective durations corresponding to the period of the sampling frequency.
Such current steering DACs are commonly used in conjunction with direct digital synthesisers, where a plurality of consecutive data samples representative of a sine waveform are generated. The data samples are converted by the current steering DAC into consecutive proportional currents, which are steered through the load resistor, across which a corresponding analogue voltage output is developed, which is representative of the sine waveform. The quality of the reconstructed analogue waveform depends fundamentally on the magnitude of the waveform errors contributed to by the resolution of the DAC. These errors can be reduced by increasing the data sampling rate at which the data samples are provided to the DAC, and also by increasing the resolution of the DAC. However, increasing the data sampling rate and the resolution of a DAC requires a corresponding increase in the word length and address range of, for example, a look-up table in the direct digital synthesiser. Accordingly, the selection of the data sampling rate and the resolution of a DAC, in general, is based on a compromise between high performance and technical and economical limitations.
A number of methods for increasing the performance of a DAC have been developed. One such method is commonly referred to as “sampled linear interpolation”. One form of sampled linear interpolation requires determining the difference between consecutive data samples received by the DAC. This is achieved by subtracting the value of the immediately previous data sample received by the DAC from the current data sample received by the DAC. The difference between the data samples is divided by an oversampling factor N into N equal data values, which are sequentially and cumulatively added to the immediately previous data sample at an oversampling rate, which is the product of the data sampling rate by the oversampling factor N. The resulting oversampled digital data represents a waveform with sampled linear interpolation between the respective data samples received by the DAC. In this method the DAC is operated at the oversampling rate, and in order to avoid large non-linearity errors due to truncation of fractional parts of the interpolated data values, the resolution of the DAC must be increased. Such a sampled linear interpolation method is disclosed in a paper entitled “High speed CMOS digital-to-analog converter with linear interpolator” by Wang, Chan and Choy published in IEEE Transactions on Consumer Electronics, Volume 46, No. 4, November 2000.
While the method disclosed by Wang, et al avoids the requirement to increase the word length of a look-up table of, for example, a direct digital synthesiser, the method of Wang requires an increase in both the DAC data sampling rate and the resolution of the DAC. The degree to which the sampling rate and the resolution of a DAC can be increased is limited by various parameters, for example, technological limits, power requirement, silicon area and, in general, cost considerations.
A DAC which would operate on the principle of sampled linear interpolation is illustrated in FIG. 1, and is indicated generally by the reference numeral 100. The prior art DAC 100 comprises a digital signal processing circuit 101, and a current steering DAC circuit 102. The digital signal processing circuit 101 receives data samples of the digital input signal into an input register 103 at a data sampling rate fs. The data samples are clocked from the input register 103 into a delay register 104 at the data sampling rate fs, where they are stored for one clock cycle of the data sampling rate fs. The data sampling rate fs is derived from a data sampling clock signal fs applied to the current steering DAC 100. A subtracting circuit 105 subtracts the value of the data sample in the delay register 104 from the value of the current data sample in the input register 103 to provide a difference value, which is the difference between the current data sample and the immediately previously received data sample. A divider circuit 106 divides the difference value by an oversampling factor N into N equal data values, one of which is applied to an interpolation data adder 107, and is cumulatively added on sequential clock cycles at an oversampling rate fos. The oversampling rate is equal to the product of the data sampling rate fs by the oversampling factor N. A frequency multiplier 108 multiplies the data sampling clock signal fs by the oversampling factor N to produce an oversampling clock signal fos.
A multiplier circuit 109 multiplies the immediately previous data sample in the delay register 104 by the oversampling factor N for providing the immediately previous data sample N times at the oversampling rate fos to an adder 110, where the current cumulative value of the data values from the interpolation data adder 107 is added to the immediately previously received data sample at the oversampling rate fos. The data values from the adder 110 are thus representative of a waveform with sampled linear interpolation between the respective data samples.
The data samples from the adder 110 are written to a DAC register 111 of the current steering DAC circuit 102 at the oversampling rate fos. A current steering DAC 112 in the current steering DAC circuit 102 sequentially converts the data samples written to the DAC register 111 into corresponding proportional current signals which are proportional to the values of the respective data samples. The proportional current signals are sequentially steered by the DAC 112 through a load resistor Rout which is coupled between an output terminal 113 of the current steering DAC circuit 102 and ground 114. The voltage appearing across the load resistor Rout on the output terminal 113 with respect to ground 114 is an analogue voltage which is representative of the digital input signal with linear interpolation between the data samples.
As discussed above, while the prior art DAC 100 of FIG. 1 avoids the requirement of having to increase the word length of the look-up table of, for example, a direct digital synthesiser, and to some extent reduces waveform errors in the reconstructed waveform, significant waveform errors are still present in the reconstructed waveform as will be discussed below with reference to FIGS. 5(a) and 5(b). Furthermore, the prior art DAC 100 of FIG. 1 requires an increase in both the DAC data sampling rate and the resolution of the DAC.
There is therefore a need for a DAC which addresses these problems of prior art DACs, and which provides a reconstructed analogue output waveform with continuous linear interpolation, and thus with substantially infinite resolution, without the need for oversampling and without having to increase the resolution of the DAC.
In frequency synthesisers the frequencies which can be synthesised without jitter from a reference frequency, where the reference frequency is being divided by a divisor, which may be an integer, a fraction or an integer and a fraction is limited. Unless the divisor divides into the frequency of the reference frequency without a remainder, the synthesised frequency will include jitter. This is undesirable, and there is therefore a need for a frequency synthesiser which addresses this problem.
The present invention is directed towards providing a method for converting a time varying digital input signal comprising consecutive data samples to an analogue voltage output signal with substantially infinite resolution. The invention is also directed towards providing a method for operating a current steering DAC for converting a time varying digital input signal comprising consecutive data samples to an analogue voltage output signal with substantially infinite resolution. The invention is also directed towards providing a DAC for converting a time varying digital input signal comprising consecutive data samples to an analogue voltage output signal of substantially infinite resolution. The invention is further directed towards providing a method and a frequency synthesiser for synthesising a frequency with jitter minimised from a reference frequency. The invention is also directed towards providing a direct digital synthesiser.